1. Field
The embodiment relates to reference voltage generator circuits, and more particularly, to a reference voltage generator circuit using a pair of PN junction devices with different current densities to generate a temperature-independent reference voltage.
2. Description of the Related Art
As a result of the recent tendency toward further reduction in size and increased portability of various systems, there has been a demand for reference voltage generator circuits capable of supplying a low, stable reference voltage to semiconductor integrated circuits. Such reference voltage generator circuits are needed especially for semiconductor integrated circuits used in IC (Integrated Circuit) cards or ID (Identification) chips which are generally not equipped with a power supply. Semiconductor integrated circuits used in these applications derive electric power from the energy of radio waves irradiated for the purpose of access and operate with a reference voltage generated from the derived power. Accordingly, if a low, stable reference voltage can be generated, then it is possible to attain a wider communicable range.
Typical reference voltage generator circuits popular in recent years utilize the energy band-gap of silicon PN junction and are referred to also as band-gap reference circuits.
The following describe exemplary reference voltage generator circuits disclosed in Japanese Unexamined Patent Publication No. 2000-35827 (paragraph nos. [0041] to and [0099] to [0118], FIGS. 1 and 2), by way of example.
FIGS. 7 and 8 are circuit diagrams each exemplifying a conventional reference voltage generator circuit.
The conventional reference voltage generator circuit shown in FIG. 7 includes two PNP bipolar transistors (hereinafter referred to merely as PNP transistors) Q10 and Q11 of which the collectors are connected to their respective bases (diode connection) and which have respective different current densities, resistors R10, R11 and R12, a differential amplifier circuit 11, and a start-up circuit 12. Each of the PNP transistors Q10 and Q11 has its collector and base connected to a ground terminal GND. The emitter of the PNP transistor Q10 is connected to the series-connected resistors R10 and R11, and the emitter of the PNP transistor Q11 is connected to the resistor R12. The other end of the resistor R11 is connected to the other end of the resistor R12. The resistors R11 and R12 have the same resistance value. The differential amplifier circuit 11 has an inverting input terminal (−) connected to the node between the resistors R10 and R11 and has a non-inverting input terminal (+) connected to the node between the resistor R12 and the emitter of the PNP transistor Q11. The output terminal of the differential amplifier circuit 11 is connected to the respective other ends of the resistors R11 and R12. The start-up circuit 12 is connected between the output terminal and non-inverting input terminal of the differential amplifier circuit 11.
In the reference voltage generator circuit configured as described above, feedback control is performed so as to make the potentials of the inverting and non-inverting input terminals of the differential amplifier circuit 11 equal to each other, thereby canceling out the temperature dependences (about −2.0 mV per ° C.) of the base-emitter voltages Vbe3 and Vbe4 of the PNP transistors Q10 and Q11 to allow a temperature-independent, stable reference voltage of about 1.25 V to be output from a terminal 13. Also, the reference voltage generator circuit is started by the start-up circuit 12 so as to prevent the input and output voltages of the differential amplifier circuit 11 from being fixed at 0 V due to the feedback control.
On the other hand, the conventional reference voltage generator circuit shown in FIG. 8 includes p-channel MOS (Metal-Oxide Semiconductor) field-effect transistors (hereinafter referred to as PMOS transistors) MP50, MP51 and MP52, n-channel MOS field-effect transistors (hereinafter referred to as NMOS transistors) MN50 and MN51, three PNP transistors Q12, Q13 and Q14 of which the collectors are connected to their respective bases, resistors R13 and R14, and a start-up circuit 14.
The PMOS transistors MP50, MP51 and MP52 have a common gate connected to the drain of the PMOS transistor MP51 and a common source connected to a power supply line Vdd. The drain of the PMOS transistor MP50 is connected to the drain of the NMOS transistor MN50, and the drain of the PMOS transistor MP51 is connected to the drain of the NMOS transistor MN51. The NMOS transistors MN50 and MN51 have a common gate connected to the drain of the NMOS transistor MN50. The source of the NMOS transistor MN50 is connected to the emitter of the PNP transistor Q12, and the source of the NMOS transistor MN51 is connected through the resistor R13 to the emitter of the PNP transistor Q13. The drain of the PMOS transistor MP52 is connected through the resistor R14 to the emitter of the PNP transistor Q14. Each of the PNP transistors Q12, Q13 and Q14 has its collector and base connected to a ground terminal GND. The start-up circuit 14 is connected between the common source of the PMOS transistors MP50, MP51 and MP52 and the drain of the PMOS transistor MP52. A reference voltage output terminal 15 is connected to the drain of the PMOS transistor MP52.
The PMOS transistors MP50, MP51 and MP52 are of the same size and constitute a current mirror circuit, and by virtue of a constant current flowing to the resistor R14 and the PNP transistor Q14, a stable reference voltage of about 1.25 V can be output from the terminal 15. In this reference voltage generator circuit, the PMOS transistors MP50 and MP51 are respectively connected in series with the NMOS transistors MN50 and MN51, thereby suppressing dependence on the supply voltage and enabling the supply of a highly accurate constant current. Also, the reference voltage generator circuit is started by the start-up circuit 14 so as to prevent the output voltage from being fixed at a stable point other than the reference voltage.
Meanwhile, a bias circuit for use in a reference voltage generator circuit and capable of lessening the supply voltage dependence is disclosed, for example, in Examined Japanese Patent Publication No. H07-27424 (FIGS. 1 and 3).